The present invention relates to a semiconductor integrated circuit device and the method of manufacture thereof; and, more particularly, the invention relates to a technique that can be effectively applied to a semiconductor integrated circuit device including nonvolatile memories, and the method of manufacture thereof.
Nonvolatile memories in which data writing and erasing can be electrically performed are widely used in various products that require memories, and they are noted for their simplicity in use since they can be overwritten without the need of removing them from, for example, a wiring board on which they are mounted. Especially, electric erasable programmable read only memories (hereinafter referred to as a xe2x80x9cflash memory (EEPROM)xe2x80x9d) allow the size of memory cells to be reduced to a size smaller than the memory cells of DRAMs (Dynamic Random Access Memory); thus, such memories are expected to be effective for use as a substitute for magnetic disks.
A flash memory (EEPROM) has a function to electrically erase, in batch, the data stored in a given range of a memory cell array (all the memory cells in the memory cell array or a given group of the memory cells). Among such flash memories (EEPROM), a demand for those having a 1-bit/1-MISFET (metal insulator semiconductor field-effect transistor) structure is drastically growing, since such devices allow higher levels of integration. In the 1-bit/1-MISFET structure, a memory cell fundamentally comprises one double-level gate MISFET. This double-level gate MISFET is formed by providing a floating gate electrode over a semiconductor substrate via a tunnel insulating film and additionally forming a control gate electrode thereon via an interlayer film. A data storing operation is performed by injecting electrons into the floating gate electrode and by drawing the electrons out from the floating gate electrode.
For flash memories (EEPROM), a structure is disclosed in Japanese Patent Laid-Open No. 306889/1996, in which floating gates are provided to transistors other than memory cells of the flash memories, and the floating gates and control gates of the transistors other than the memory cells are connected via metal wirings.
Also, a structure and the manufacturing method thereof are disclosed in, for example, Japanese Patent Laid-open NO. 25069/1990, wherein a first gate oxide film, a first gate electrode, a second gate oxide film, a second gate electrode and a high-melting point silicide film are deposited as a common structure for both nonvolatile memory cells having a double gate structure and MOS transistors; and, in the MOS transistor, the first gate electrode and the second gate electrode are connected via a contact hole formed within the second gate oxide film.
As another example, there is a structure and the manufacturing method thereof disclosed in, for example, Japanese Patent Laid-Open No. 34977/1988 which is a publication of a patent application corresponding to U.S. Pat. No. 4,780,431, in which the same gate structure is used for EEPROM nonvolatile memory cells and associated transistors; and, for the associated transistors, a first silicon layer and a second silicon layer formed thereon are connected by etching portion of an oxide thin film provided between them.
As still another example, there is a nonvolatile semiconductor memory device and the manufacturing method thereof disclosed in, for example, Japanese Patent Application Laid-Open No. 298314/1996, in which, after sequentially forming a first polysilicon film and a second gate oxide film from the bottom over a memory cell region and a peripheral circuit region, the second gate insulating film within the peripheral circuit region is selectively removed, and a second polysilicon film is then deposited.
The inventor of the present invention has discovered, however, that the above-mentioned techniques for formation of a semiconductor integrated circuit device including nonvolatile memories have the following problems.
That is, where the double-level gate electrode structure is employed for the field-effect transistors of the peripheral circuitry, the resistivity of the gate electrodes cannot be reduced according to the types of the field-effect transistors by simply providing contact holes for connecting between the two layers of the gate electrode; and so, as the through current of the whole flash memory (EEPROM) increases, the power consumption also increases.
When attempting to change the layout of each of the components (i.e. contact holes connecting the source and drain to a first-level wiring layer) of a field-effect transistor to be used as a peripheral circuit in order to solve the above problem, a desirable layout can hardly be obtained. That is, there is a problem in that it is difficult to represent a device structure without encountering inconveniences in circuit designing.
An object of the present invention is to provide a technique which provides for a the reduction in the resistivity of the gate electrodes of the peripheral circuits of a semiconductor integrated circuit device including nonvolatile memories.
Another object of the present invention is to provide a technique which provides for a reduction in the power consumption of a semiconductor integrated circuit device including nonvolatile memories.
Still another object of the present invention is to provide a technique which allows the layout of the devices intended for peripheral circuits of a semiconductor integrated circuit device including nonvolatile memories to be performed more easily.
Yet another object of the present invention is to provide a technique which allows the transition to be made more easily from the circuit design of peripheral circuits to the device design of a semiconductor integrated circuit device having nonvolatile memories.
The above and other objects and novel features of the present invention will be apparent from the following description when taken in conjunction with the attached drawings.
The summary of representative aspects of the invention disclosed herein will be briefly explained as follows.
In accordance with the present invention, the gate electrode of a field-effect transistor for a peripheral circuit is constituted by the same gate electrode structure as that of nonvolatile memory cells having a double-level gate electrode structure, and a hole for the connection between the two layers of the gate electrode of the field-effect transistor for the peripheral circuit is formed at a location which two-dimensionally overlaps an active area within the plane of the gate electrode.
Moreover, in accordance with the present invention, the gate electrode of a field-effect transistor for a peripheral circuit is constituted by the same gate electrode structure as that of nonvolatile memory cells having a double-level gate electrode structure, and a hole for the connection between the two layers of the gate electrode of the field-effect transistor for a peripheral circuit is formed at each of a location which two-dimensionally overlaps an active area and a location which two-dimensionally overlaps an isolation area within the planes of the gate electrode.
Furthermore, in accordance with the present invention, the gate electrode of a field-effect transistor for a peripheral circuit is constituted by the same gate electrode structure as that of nonvolatile memory cells having a double-level gate electrode structure, and a hole for the connection between the two layers of the gate electrodes of the field-effect transistor for the peripheral circuit is formed at a location which two-dimensionally overlaps an isolation area within the planes of the gate electrode.
Also, in accordance with the present invention, the gate electrodes of first and second field-effect transistors for a peripheral circuit are constituted by the qame gate electrode structure as that of nonvolatile memory cells having a double-level gate electrode structure, and a hole for the connection between the two layers of the gate electrode of the first field-effect transistor is formed at a location which two-dimensionally overlaps an active area within the planes of the gate electrode, and a hole for the connection between the two layers of the gate electrode of the second field-effect transistor is formed at a location which two-dimensionally overlaps an isolation area within the planes of the gate electrodes. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor. The gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.
Furthermore, in accordance with the present invention, the first gate electrode of the double-level gate electrode is made of polycrystalline silicon, and the second gate electrode includes a higb-melting point metal silicide film or a high-melting point metal film.